Reference. Security Verification of Low-Trust Architectures
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- Sequestered Encryption: A Hardware Technique for Comprehensive Data Privacy (2022)
- Frequency Throttling Side-Channel Attack (2022)
- CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL (2022)
- Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86 (2022)
- JasperGold Security Path Verification (2022)
- Hardware-Software Contracts for Secure Speculation (2021)
- Hardware Information Flow Tracking (2021)
- Massively Parallel Ultrafast Random Bit Generation with a Chip-scale Laser (2021)
- DOLMA: Securing Speculation with the Principle of Transient Non-Observability (2021)
- CIPHERLEAKS: Breaking Constant-time Cryptography on AMD SEV via the Ciphertext Side Channel (2021)
- A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors (2020)
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- Keystone: An Open Framework for Architecting Trusted Execution Environments (2020)
- Drop by Drop you break the rock - Exploiting generic vulnerabilities in Lattice-based PKE/KEMs using EM-based Physical Attacks (2020)
- A New Side-Channel Vulnerability on Modern Computers by Exploiting Electromagnetic Emanations from the Power Management Unit (2020)
- Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution (2020)
- Practical Attacks on Reduced-Round AES (2019)
- MI6: Secure Enclaves in a Speculative Out-of-Order Processor (2019)
- Processor Hardware Security Vulnerabilities and Their Detection by Unique Program Execution Checking (2019)
- IODINE: Verifying Constant-Time Execution of Hardware (2019)
- Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data (2019)
- Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing (2019)
- One&Done: A Single-Decryption EM-Based Attack on OpenSSL's Constant-Time Blinded RSA (2018)
- Dieharder: A Random Number Test Suite (2018)
- HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security (2018)
- A Formally Verified Cryptographic Extension to a RISC-V Processor (2018)
- Clepsydra: Modeling timing flows in hardware designs (2017)
- Register transfer level information flow tracking for provably secure hardware design (2017)
- The QARMA Block Cipher Family. Almost MDS Matrices Over Rings With Zero Divisors, Nearly Symmetric Even-Mansour Constructions With Non-Involutory Central Rounds, and Search Heuristics for Low-Latency S-Boxes (2017)
- Secure Information Flow Verification with Mutable Dependent Types (2017)
- Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis (2017)
- A new approach of elliptic curve Diffie-Hellman key exchange (2017)
- Design and Implementation of the Ascend Secure Processor (2017)
- Recommendation for Pair-wise Key-Establishment Schemes Using Discrete Logarithm Cryptography (2017)
- Intel SGX Explained (2016)
- Sanctum: Minimal Hardware Extensions for Strong Software Isolation (2016)
- Intel Software Guard Extensions: Introduction and Open Research Challenges (2016)
- An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations (2016)
- The SIMON and SPECK lightweight block ciphers (2015)
- Last-Level Cache Side-Channel Attacks are Practical (2015)
- A Hardware Design Language for Timing-Sensitive Information-Flow Security (2015)
- Imperfect Forward Secrecy: How Diffie-Hellman Fails in Practice (2015)
- The Elliptic Curve Diffie-Hellman (ECDH) (2015)
- A True Random Number Generator Algorithm from Digital Camera Image Noise for Varying Lighting Conditions (2015)
- On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models (2014)
- A 0.43pJ/bit true random number generator (2014)
- Leveraging Gate-Level Properties to Identify Hardware Timing Channels (2014)
- Goodness-of-Fit and Randomness Tests for the Sun’s Emissions True Random Number Generator (2014)
- Innovative instructions and software model for isolated execution (2013)
- A chaos based integrated jitter booster circuit for true random number generators (2013)
- Innovative Technology for CPU based Attestation and Sealing (2013)
- Jasper Case Study on Formally Verifying Secure On-Chip Datapaths (2013)
- Entropy Harvesting from Physical Sensors (2013)
- High-speed Random Number Generator for Section Key Generation in Encryption Devices (2013)
- Performance of Random Number Generators Using Noise-Based Superluminescent Diode and Chaos-Based Semiconductor Lasers (2013)
- A secure processor architecture for encrypted computation on untrusted programs (2012)
- Contactless Electromagnetic Active Attack on Ring Oscillator-based True Random Number Generator (2012)
- Proving noninterference for a while-language using small-step operational semantics (2011)
- On the Security of Oscillator-Based Random Number Generators (2010)
- Scalable Architectural Support for Trusted Software (2010)
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- Mixing type checking and symbolic execution (2010)
- A 500 mV 650 pW Random Number Generator in 130 nm CMOS for a UWB Localization System (2010)
- Advanced Encryption Standard (AES) (2009)
- Declassification: Dimensions and principles (2009)
- Complete information flow tracking from the gates up (2009)
- Bias-free true random-number generator (2009)
- Chaos Based Generation of True Random Bits (2009)
- Side-channel Analysis of Cryptographic Software via Early-terminating Multiplications (2009)
- A 3 μW CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation (2008)
- A Novel Key Exchange Protocol Based on RSA-OAEP (2008)
- Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings (2008)
- Gradual Release: Unifying Declassification, Encryption and Key Release Policies (2007)
- Provably secure authenticated group Diffie-Hellman key exchange (2007)
- Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core (2006)
- RSA Key Exchange for the Secure Shell (SSH) Transport Layer Protocol (2006)
- Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions (2005)
- Timing Attacks on RSA: Revealing Your Secrets through the Fourth Dimension (2005)
- TrustZone : Integrated Hardware and Software Security (2004)
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- AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing (2003)
- Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts (2003)
- An Overview of Hardware Security Modules (2002)
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- Public Key Infrastructure Overview (2001)
- Mixed-signal Map-Configurable Integrated Chaos Generator for Chaotic Communications (2001)
- A Truly Random Number Generator Based on Thermal Noise (2001)
- A noise-based IC random number generator for applications in cryptography (2000)
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- Diffie-Hellman Key Agreement Method (1999)
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